Low Power Multiplier Optimized by Modified Partial Product Summation

Multiplication is a commonly used operation of Digital signal processing. The objective of a good multiplier is to provide a physically compact, high speed and a low power consuming chip. A low power multiplier using a dynamic range determination unit and a modified upper/lower left-to-right in the partial product summation is designed. The proposed multiplier is based on the modified booth algorithm and parallel operation of partial product summation which accelerates multiplication speed. Prior to executing a multiplication, effective dynamic ranges of the two input data are estimated by the dynamic range determination unit to determine that these input data with smaller and larger dynamic range are multiplier and multiplicand for booth decoding. An efficient radix-4 recoding logic generates the partial products in a left-to-right order. The partial products are split into upper and lower groups. The partial products in high precision have high chance of being zero. The upper/lower left-to-right structure is modified by moving the correction bits from upper part to lower part of partial product summation unit to reduce switching power. Additionally, low power adder cells instead of the conventional full adders are added in upper/ lower parts of partial product summation to conserve power. The proposed and conventional multipliers are implemented and simulated using Modelsim, Microwind and Xilinx. The simulated results demonstrate that the proposed multiplier consumes the least power than the conventional ones.